VHDL Lab

Simulate with GHDL and synthesize with Yosys, nothing to install

Write your code or open one of the Examples, then press Simulate or Synthesize.

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No synthesis yet.

No synthesis yet.

Help

  1. Code: put the design and the testbench in separate files (the “+ File” button) or upload .vhd files. File order does not matter. Your work is saved automatically in this browser.
  2. Simulate: pick the testbench (an entity without ports) and a stop time such as 500ns. If your clock runs forever, the simulation stops at that time. At most 1ms.
  3. Waveform: mouse wheel to zoom, drag to pan, click to place the cursor, double-click to see the whole run. Click a vector's name to change its radix (hex, binary, decimal). The .ghw file also opens in GTKWave.
  4. Synthesize: pick the top entity of your design. Files that hold only testbenches are left out.
    • RTL schematic: the circuit in generic blocks (gates, multiplexers, adders, flip-flops), like Vivado's Elaborated Design.
    • Gates: the same circuit mapped to simple gates, to compare with your Proteus circuit.
    • FPGA: synthesis for Xilinx 7-series FPGAs (such as Artix-7) with LUT and flip-flop counts. It is a different tool, so the numbers can differ a little from Vivado's.
  5. Limits: a simulation may run for 15 seconds and a synthesis for 40. foreign and VHPI are not allowed. Enumerated types (such as FSM states) show by name in the waveform. Names in the waveform are lower case.